Optimized Implementation of Real-time Image Processing Algorithms on Field Programmable Gate Arrays

We present the Algorithm Architecture “Adequation” methodology for the optimized implementation of real-time image processing algorithms on field programmable gate arrays. This methodology is based on a single factorized graphs model, used from the algorithm specification down to the architecture implementation, through optimizations expressed in terms of defactorization transformations. A simple image processing example is presented to illustrate the methodology.